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FEATURES Pin-Compatible 12- and 14-Bit DACs Serial Input, Voltage Output Maximum Output Voltage Range of 10 V Data Readback 3-Wire Serial Interface Clear Function to a User-Defined Voltage Power-Down Function Serial Data Output for Daisy-Chaining 16-Lead TSSOP Packages APPLICATIONS Industrial Automation Automatic Test Equipment Process Control General-Purpose Instrumentation
Serial Input, Voltage Output 12-/14-Bit DACs AD5530/AD5531
GENERAL DESCRIPTION
The AD5530 and AD5531 are single 12-/14-bit serial input, voltage output DACs, respectively. They utilize a versatile 3-wire interface that is compatible with SPITM, QSPITM, MICROWIRETM, and DSP interface standards. Data is presented to the part in the format of a 16-bit serial word. Serial data is available on the SDO pin for daisy-chaining purposes. Data readback allows the user to read the contents of the DAC register via the SDO pin. The DAC output is buffered by a gain of 2 amplifier and referenced to the potential at DUTGND. LDAC may be used to update the output of the DAC asynchronously. A power-down (PD) pin allows the DAC to be put into a low power state, and a CLR pin allows the output to be cleared to a user-defined voltage, the potential at DUTGND. The AD5530 and AD5531 are available in 16-lead TSSOP packages.
FUNCTIONAL BLOCK DIAGRAM
VSS VDD
AD5530/AD5531
REFIN - + DAC REGISTER R 12-/14-BIT DAC + VOUT R R DUTGND SHIFT REGISTER POWER-DOWN CONTROL LOGIC GND SCLK SYNC SDO CLR PD - R REFAGND LDAC RBEN
SDIN
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation.
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Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) Analog Devices, Inc., 2002
AD5530/AD5531-SPECIFICATIONS1 C = 220 pF to GND. All specifications T
Parameter ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient2 REFERENCE INPUTS2 Reference Input Range DC Input Resistance Input Current DUTGND INPUT DC Input Impedance Max Input Current Input Range O/P CHARACTERISTICS Output Voltage Swing Short Circuit Current Resistive Load Capacitive Load DC Output Impedance
2 2
(VDD = +15 V 10%; VSS = -15 V 10%; GND = 0 V; RL = 5 k and L MIN to TMAX, unless otherwise noted.)
Unit Test Conditions/Comments
AD5530 12 1 1 2 2 1 0.5 10 0/5 100 1 60 0.3 -4/+4 10 15 5 1200 0.5 2.4 0.8 10 10 0.4 +15/-15 110 100 2 2 150
AD5531 14 2 1 8 8 4 0.5 10 0/5 100 1 60 0.3 -4/+4 10 15 5 1200 0.5 2.4 0.8 10 10 0.4 +15/-15 110 100 2 2 150
Bits LSB max LSB max LSB max LSB max LSB typ ppm FSR/C typ ppm FSR/C max V min/V max M typ A max k typ mA typ V min/V max V max mA max k min pF max max V min V max A max pF max V max V nom dB typ dB typ mA max mA max A max
Guaranteed Monotonic Over Temperature Typically within 1 LSB Typically within 1 LSB
Max Output Range 10 V Per Input. Typically 20 nA.
Max Output Range 10 V
To 0 V To 0 V
DIGITAL I/O VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance2 SDO VOL Output Low Voltage POWER REQUIREMENTS VDD/VSS Power Supply Sensitivity Full Scale/VDD Full Scale/VSS IDD ISS IDD in Power-Down
Total for All Pins 3 pF Typ ISINK = 1 mA 10% For Specified Performance
Outputs Unloaded Outputs Unloaded Typically 50 A
NOTES 1 Temperature range for B Version: -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
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SPECIFICATIONS1 (V
Parameter
DD = +12 V 10%; VSS = -12 V 10%; GND = 0 V; RL = 5 k and CL = 220 pF to GND; TA = TMIN to TMAX, unless otherwise noted.)
AD5530/AD5531
Test Conditions/Comments
AD5530 12 1 1 2 2 1 0.5 10 0/4.096 100 1 60 0.3 -3/+3
2
AD5531 14 2 1 8 8 4 0.5 10 0/4.096 100 1 60 0.3 -3/+3 8.192 15 5 1200 0.5 2.4 0.8 10 10 0.4 +12/-12 110 100 2 2 150
Unit Bits LSB max LSB max LSB max LSB max LSB typ ppm FSR/C typ ppm FSR/C max V min/V max M typ A max k typ mA typ V min/V max V max mA max k min pF max max V min V max A max pF max V max V nom dB typ dB typ mA max mA max A max
ACCURACY Resolution Relative Accuracy Differential Nonlinearity Zero-Scale Error Full-Scale Error Gain Error Gain Temperature Coefficient2 REFERENCE INPUTS2 Reference Input Range DC Input Resistance Input Current DUTGND INPUT2 DC Input Impedance Max Input Current Input Range O/P CHARACTERISTICS Output Voltage Swing Short Circuit Current Resistive Load Capacitive Load DC Output Impedance
Guaranteed Monotonic Over Temperature Typically within 1 LSB Typically within 1 LSB
Max Output Range 8.192 V Per Input. Typically 20 nA.
Max Output Range 8.192 V
8.192 15 5 1200 0.5 2.4 0.8 10 10 0.4 +12/-12 110 100 2 2 150
To 0 V To 0 V
DIGITAL I/O VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance2 SDO VOL Output Low Voltage POWER REQUIREMENTS VDD /VSS Power Supply Sensitivity Full Scale/VDD Full Scale/VSS IDD ISS IDD in Power-Down
Total for All Pins 3 pF Typ ISINK = 1 mA 10% For Specified Performance
Outputs Unloaded Outputs Unloaded Typically 50 A
NOTES 1 Temperature range for B Version: -40C to +85C. 2 Guaranteed by design, not subject to production test. Specifications subject to change without notice.
AC PERFORMANCE CHARACTERISTICS C = 220 pF to GND. All specifications T
Parameter DYNAMIC PERFORMANCE Output Voltage Settling Time Slew Rate Digital-to-Analog Glitch Impulse Digital Feedthrough Output Noise Spectral Density @ 1 kHz A 20 1.3 120 0.5 100 Unit s typ V/s typ nV-s typ nV-s typ nV/(Hz)1/2typ
(VDD = 10.8 V to 16.5 V, VSS = -10.8 V to -16.5 V; GND = 0 V; RL = 5 k and L MIN to TMAX, unless otherwise noted.)
Test Conditions/Comments Full-Scale Change to 1/2 LSB. DAC Latch Contents alternately loaded with all 0s and all 1s. DAC Latch alternately loaded with 0FFF Hex and 1000 Hex. Not dependent on load conditions. Effect of Input Bus Activity on DAC Output Under Test All 1s Loaded to DAC
Specifications subject to change without notice. Guaranteed by design, not subject to production test.
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AD5530/AD5531 STANDALONE TIMING CHARACTERISTICS1, 2 (V
Parameter fMAX t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12
1 2
DD = 10.8 V to 16.5 V, VSS = -10.8 V to -16.5 V; GND = 0 V; RL = 5 k and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
Limit at TMIN, TMAX 7 140 60 60 50 40 50 40 15 5 50 5 50
Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min
Description SCLK Frequency SCLK Cycle Time SCLK Low Time SCLK High Time SYNC to SCLK Falling Edge Setup Time SCLK Falling Edge to SYNC Rising Edge Min SYNC High Time Data Setup Time Data Hold Time SYNC High to LDAC Low LDAC Pulsewidth LDAC High to SYNC Low CLR Pulsewidth
Guaranteed by design. Not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL +VIH)/2. Specifications subject to change without notice.
t1
SCLK
t3 t2 t5
t4
SYNC
t6
MSB
t7
DB15 DB14
t8
LSB DB0
SDIN
DB11
t9
LDAC*
t11 t10 t12
CLR *LDAC MAY BE TIED PERMANENTLY LOW IF REQUIRED
Figure 1. Timing Diagram for Standalone Mode
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AD5530/AD5531
DD = 10.8 V to 16.5 V, VSS = -10.8 V to -16.5 V; VSS = -15 V 10%; GND = 0 V; RL = 5 k and CL = 220 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.)
DAISY-CHAINING AND READBACK TIMING CHARACTERISTICS1, 2, 3 (V
Parameter Limit at TMIN, TMAX 2 500 200 200 50 40 50 40 15 50 130 50 50 50 100 Unit MHz max ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns max ns min ns min ns min
Description SCLK Frequency SCLK Cycle Time SCLK Low Time SCLK High Time SYNC to SCLK Falling Edge Setup Time SCLK Falling Edge to SYNC Rising Edge Min SYNC High Time Data Setup Time Data Hold Time CLR Pulsewidth SCLK Falling Edge to SDO Valid SCLK Falling Edge to SDO Invalid RBEN to SCLK Falling Edge Setup Time RBEN Hold Time RBEN Falling Edge to SDO Valid
fMAX t1 t2 t3 t4 t5 t6 t7 t8 t12 t13 t14 t15 t16 t17
1 2
Guaranteed by design. Not production tested. Sample tested during initial release and after any redesign or process change that may affect this parameter. All input signals are measured with tr = tf = 5 ns (10% to 90% of V DD) and timed from a voltage level of (V IL + VIH)/2. 3 SDO; RPULLUP = 5 k, CL = 15 pF. Specifications subject to change without notice.
t1
SCLK
t3 t2
t4
SYNC
t5
t6
MSB
t7
DB15 DB14
t8
LSB DB0
SDIN
DB11
t13
SDO (DAISY CHAINING)
MSB DB15
t14
DB11
LSB DB0
t15
RBEN
t16 t13
0 MSB 0 RB13
t17
SDO (READBACK)
t14
RB0 LSB
Figure 2. Timing Diagram for Daisy-Chaining and READBACK Mode
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AD5530/AD5531
ABSOLUTE MAXIMUM RATINGS*
(TA = 25C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V, +17 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . +0.3 V, -17 V Digital Inputs to GND . . . . . . . . . . . . . -0.3 V to VDD +0.3 V SDO to GND . . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +6.5 V REFIN to REFAGND . . . . . . . . . . . . . . . . . . . . -0.3 V, +17 V REFIN to GND . . . . . . . . . . . . . . . . VSS - 0.3 V, VDD +0.3 V REFAGND to GND . . . . . . . . . . . . . VSS - 0.3 V, VDD +0.3 V DUTGND to GND . . . . . . . . . . . . . . VSS - 0.3 V, VDD +0.3 V Operating Temperature Range Industrial (B Version) . . . . . . . . . . . . . . . . -40C to +85C
Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature (TJ MAX) . . . . . . . . . . 150C Package Power Dissipation . . . . . . . . . . . . . . (TJ MAX - TA)/JA Thermal Impedance JA TSSOP (RU-16) . . . . . . . . . . . . . . . . . . . . . . . . 150.4C/W Lead Temperature (Soldering 10s) . . . . . . . . . . . . . . . . 300C IR Reflow, Peak Temperature (< 20 sec) . . . . . . . . . . . . 235C
*
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ORDERING GUIDE
Model
Temperature Range
Resolution 12 14
INL (LSBs) 1 2
DNL(LSBs) 1 1
Package Option* RU-16 RU-16
AD5530BRU -40C to +85 C AD5531BRU -40C to +85 C
*RU = Thin Shrink Small Outline Package.
PIN CONFIGURATION
REFAGND 1 REFIN 2 LDAC 3 SDIN 4
16 VDD 15 VOUT
13 VSS TOP VIEW SYNC 5 (Not to Scale) 12 NC
AD5530/ AD5531
14 DUTGND
RBEN 6 SCLK 7 SDO 8
11 GND 10 PD 9
CLR
NC = NO CONNECT
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD5530/AD5531 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
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AD5530/AD5531
PIN FUNCTION DESCRIPTIONS
Pin 1 2 3
Mnemonic REFAGND REFIN LDAC
Function For bipolar 10 V output range, this pin should be tied to 0 V. This is the voltage reference input for the DAC. Connect to external +5 V reference for specified bipolar 10 V output. Load DAC logic input (active low). When taken low, the contents of the shift register are transferred to the DAC register. LDAC may be tied permanently low enabling the outputs to be updated on the rising edge of SYNC. Serial data input. This device accepts 16-bit words. Data is clocked into the input register on the falling edge of SCLK. Active low control input. Data is clocked into the shift requester on the falling edges of SCLK. Active low readback enable function. This function allows the contents of the DAC register to be read. Data from the DAC register will be shifted out on SDO pin on each rising edge of SCLK. Clock input. Data is clocked into the input register on the falling edge of SCLK. Serial data out. This pin is used to clock out the serial data previously written to the input shift register or may be used in conjunction with RBEN to read back the data from the DAC register. This is an open drain output; it should be pulled high with an external pull-up resistor. In standalone mode, SDO should be tied to GND or left high impedance. Level sensitive, active low input. A falling edge of CLR resets VOUT to DUTGND. The contents of the registers are untouched. This allows the DAC to be put into a power-down state. Ground reference Do not connect anything to this pin. Negative analog supply voltage, -12 V 10% or -15 V 10% for specified performance. VOUT is referenced to the voltage applied to this pin. DAC output Positive analog supply voltage, +12 V 10% or +15 V 10% for specified performance.
Gain Error
4 5 6 7 8
SDIN SYNC RBEN SCLK SDO
9 10 11 12 13 14 15 16
CLR PD GND NC VSS DUTGND VOUT VDD
TERMINOLOGY Relative Accuracy
Relative accuracy or endpoint linearity is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function.
Differential Nonlinearity
Gain error is the difference between the actual and ideal analog output range, expressed as a percent of the full-scale range. It is the deviation in slope of the DAC transfer characteristic from ideal.
Output Voltage Settling Time
Differential nonlinearity is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A specified differential nonlinearity of 1 LSB maximum ensures monotonicity.
Zero-Scale Error
This is the amount of time it takes for the output to settle to a specified level for a full-scale input change.
Digital-to-Analog Glitch Impulse
Zero-scale error is a measure of the output error when all 0s are loaded to the DAC latch.
Full-Scale Error
Digital-to-analog glitch impulse is the impulse injected into the analog output when the input code in the DAC register changes state. It is specified as the area of the glitch in nV-s and is measured when the digital input code is changed by 1 LSB at the major carry transition.
Digital Feedthrough
This is the error in DAC output voltage when all 1s are loaded into the DAC latch. Ideally the output voltage, with all 1s loaded into the DAC latch, should be 2 VREF - 1 LSB.
Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital inputs of the DAC, but is measured when the DAC output is not updated. It is specified in nV-s and is measured with a full-scale code change on the data bus, i.e., from all 0s to all 1s and vice versa.
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AD5530/AD5531-Typical Performance Characteristics
1 0.8 0.6 0.4 0.2 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = +25 C
1 0.75 0.5 0.25
LSB
VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = +25 C
LSB
0 -0.2 -0.4
0
-0.25 -0.5
-0.6 -0.8 -1 0 500 1000 1500 2000 code 2500 3000 3500 4000
-0.75 -1
0
2000
4000
6000
8000 code
10000 12000 14000 16000
TPC 1. AD5530 Typical INL Plot
TPC 4. AD5531 Typical DNL Plot
0.5 0.4 0.3 0.2 0.1
LSB
2.0 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = +25 C
ERROR - LSBs
1.5 1.0 0.5 0 -0.5 -1.0
VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V
0 -0.1 -0.2 -0.3 -0.4 -0.5 0 500 1000 1500 2000 code 2500 3000 3500 4000
-1.5 -2.0 -40
-20
0
20
40
60
80
TEMPERATURE - C
TPC 2. AD5530 Typical DNL Plot
TPC 5. AD5531 Typical INL Error vs. Temperature
2 1.5 1 0.5
LSB
1.0
VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = +25 C
ERROR - LSBs
0.8 0.6 0.4 0.2 0 -0.2 -0.4
VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V
0 -1 -0.3
-0.6
-1.5 -2
-0.8
0
2000
4000
6000
8000 code
10000 12000 14000 16000
-1.0 -40
-20
0
20
40
60
80
TEMPERATURE - C
TPC 3. AD5531 Typical INL Plot
TPC 6. AD5531 Typical DNL Error vs. Temperature
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AD5530/AD5531
3 VDD = +15V VSS = -15V REFAGND = 0V TA = +25 C 0.02 0.03 2 POSITIVE INL
ERROR - LSBs
-40 C
1
IDD - mA
0 NEGATIVE INL -1
+25 C
+85 C
0.01
-2
-3 2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0
10
11
12
13
14
15
16
17
REFIN VOLTAGE - V
SUPPLY VOLTAGE - V
TPC 7. AD5531 Typical INL Error vs. Reference Voltage
TPC 10. IDD in Power-Down vs. Supply
0 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V
12
-0.5
8
ERROR - LSBs
4
VOUT - V
-1.0
0
-1.5
-4 5
-2.0
s/div
-8
VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = +25 C
-2.5 -40
-20
0
20
40
60
80
-12
0 TIME - s
TEMPERATURE - C
TPC 8. Typical Full-Scale and Offset Error vs. Temperature
TPC 11. Settling Time
1.50
0
1.45 +85 C
CURRENT - mA
-0.02 -0.04 -0.06
1.40 VOUT - V +25 C
1.35
-0.08 -0.10 -0.12 -0.14 VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = +25 C TIME - 750ns/DIV
-40 C 1.30
1.25
1.20
10
11
12
13
14
15
16
17
-0.16
VDD/V SS - V
TPC 9. IDD vs. VDD / VSS
TPC 12. Typical Digital-to-Analog Glitch Impulse
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AD5530/AD5531
VDD = +15V VSS = -15V REFIN = +5V REFAGND = 0V TA = +25 C
REFIN 12-/14-BIT DAC OUTPUT
14 LDAC
VOUT
DAC REGISTER 14
PD
2V/DIV
SYNC
SYNC REGISTER 14
2V/DIV
SDIN 16-BIT SHIFT REGISTER SDO
TPC 13. Typical Power-Down Time
Figure 4. Simplified Serial Interface
GENERAL DESCRIPTION DAC Architecture
Data written to the part via SDIN is available on the SDO pin 16 clocks later if the readback function is not used. SDO data is clocked out on the falling edge of the serial clock with some delay.
PD Function
The AD5530/AD5531 are pin-compatible 12-/14-bit DACs. The AD5530 consists of a straight 12-bit R-2R voltage mode DAC, while the AD5531 consists of a 14-bit R-2R section. Using a +5 V reference connected to the REFIN pin and REFAGND tied to 0 V, a bipolar 10 V voltage output results. The DAC coding is straight binary.
Serial Interface
The PD pin allows the user to place the device into power-down mode. While in this mode, power consumption is at a minimum; the device draws only 50A of current. The PD function does not affect the contents of the DAC register.
READBACK Function
Serial data on the SDIN input is loaded to the input register under the control of SCLK, SYNC, and LDAC. A write operation transfers a 16-bit word to the AD5530/AD5531. Figures 1 and 2 show the timing diagrams. Figure 3 shows the contents of the input shift register. Twelve or 14 bits of the serial word are data bits; the rest are don't cares.
DB15 (MSB) DATA BITS DB0 (LSB) X X D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 X X
The AD5530/AD5531 allows the data contained in the DAC register to be read back if required. The pins involved are the RBEN and SDO (serial data out). When RBEN is taken low, on the next falling edge of SCLK, the contents of the DAC register are transferred to the shift register. RBEN may be used to frame the readback data by leaving it low for 16 clock cycles, or it may be asserted high after the required hold time. The shift register contains the DAC register data and this is shifted out on the SDO line on each falling edge of SCLK with some delay. This ensures the data on the serial data output pin is valid for the falling edge of the receiving part. The two MSBs of the 16-bit word will be `0's.
CLR Function
Figure 3a. AD5530 Input Shift Register Contents
DB15 (MSB) DATA BITS DB0 (LSB) X X D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Figure 3b. AD5531 Input Shift Register Contents
The serial word is framed by the signal, SYNC. After a high to low transition on SYNC, data is latched into the input shift register on the falling edges of SCLK. There are two ways in which the DAC register and output may be updated. The LDAC signal is examined on the falling edge of SYNC; depending on its status, either a synchronous or asynchronous update is selected. If LDAC is low, then the DAC register and output are updated on the low to high transition of SYNC. Alternatively, if LDAC is high upon sampling, the DAC register is not loaded with the new data on a rising edge of SYNC. The contents of the DAC register and the output voltage will be updated by bringing LDAC low any time after the 16-bit data transfer is complete. LDAC may be tied permanently low if required. A simplified diagram of the input loading circuitry is illustrated in Figure 4.
The falling edge of CLR causes VOUT to be reset to the same potential as DUTGND. The contents of the registers remain unchanged, so the user can reload the previous data with LDAC after CLR is asserted high. Alternatively, if LDAC is tied low, the output will be loaded with the contents of the DAC register automatically after CLR is brought high.
Output Voltage
The DAC transfer function is as follows:
VOUT = 2 [2 x REFIN - REFAGND x

D 2
N

+ 2 x REFAGND - REFIN ] - DUTGND
where: D is the decimal data word loaded to the DAC register, N is the resolution of the DAC.
Bipolar Configuration
Figure 5 shows the AD5530/AD5531 in a bipolar circuit configuration. REFIN is driven by the AD586, 5 V reference, while the REFAGND and DUTGND pins are tied to GND. This results in a bipolar output voltage ranging from -10 V to +10 V. Resistor R1 is provided (if required) for gain adjust. Figure 6 shows the transfer function of the DAC when REFAGND is tied to 0 V. REV. 0
-10-
AD5530/AD5531
+15V
ADSP-2101/ ADSP-2103*
2 6 8 AD586 C1 1F 5 R1 10k REFIN
AD5530/ AD5531*
FO LDAC SYNC SDIN SCLK
VOUT VOUT
VOUT (-10V TO +10V)
AD5530/ AD5531*
DUTGND REFAGND GND SIGNAL GND -15V
TFS DT SCLK
4
*ADDITIONAL PINS OMITTED FOR CLARITY
SIGNAL GND
VSS
Figure 7. AD5530/AD5531 to ADSP-21xx Interface
AD5530/AD5531 to 8051 Interface
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 5. Bipolar 10 V Operation
2 REFIN
A serial interface between the AD5530/AD5531 and the 8051 is shown in Figure 8. TXD of the 8051 drives SCLK of the AD5530/ AD5531, while RXD drives the serial data line, SDIN. P3.3 and P3.4 are bit-programmable pins on the serial port and are used to drive SYNC and LDAC respectively. The 8051 provides the LSB of its SBUF register as the first bit in the data stream. The user will have to ensure that the data in the SBUF register is arranged correctly as the DAC expects MSB first.
DAC OUTPUT VOLTAGE
0V
80C51/80L51*
AD5530/ AD5531*
LDAC SYNC SDIN SCLK
P3.4 P3.3 RXD
-2 REFIN
DAC INPUT CODE 000 001
(3)FFF
TXD
Figure 6. Output Voltage vs. DAC Input Codes (Hex)
MICROPROCESSOR INTERFACING
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 8. AD5530/AD5531 to 8051 Interface
Microprocessor interfacing to the AD5530/AD5531 is via a serial bus that uses standard protocol compatible with microcontrollers and DSP processors. The communications channel is a 3-wire (minimum) interface consisting of a clock signal, a data signal, and a synchronization signal. The AD5530/AD5531 requires a 16-bit data word with data valid on the falling edge of SCLK. For all the interfaces, the DAC output update may be done automatically when all the data is clocked in or asynchronously under the control of LDAC. The contents of the DAC register may be read using the readback function. RBEN is used to frame the readback data, which is clocked out on SDO. The following figures illustrate these DACs interfacing with a simple 4-wire interface. The serial interface of the AD5530/AD5531 may be operated from a minimum of three wires.
AD5530/AD5531 to ADSP-21xx
When data is to be transmitted to the DAC, P3.3 is taken low. Data on RXD is clocked out of the microcontroller on the rising edge of TXD and is valid on the falling edge. As a result no glue logic is required between this DAC and microcontroller interface. The 8051 transmits data in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. As the DAC expects a 16-bit word, P3.3 must be left low after the first 8 bits are transferred. After the second byte has been transferred, the P3.3 line is taken high. The DAC may be updated using LDAC via P3.4 of the 8051.
AD5530/AD5531 to MC68HC11 Interface
Figure 9 shows an example of a serial interface between the AD5530/AD5531 and the MC68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC, while the MOSI output drives the serial data lines, SDIN. SYNC is driven from one of the port lines, in this case PC7.
MC68HC11*
An interface between the AD5530/AD5531 and the ADSP-21xx is shown in Figure 7. In the interface example shown, SPORT0 is used to transfer data to the DAC. The SPORT control register should be configured as follows: internal clock operation, alternate framing mode; active low framing signal. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. As the data is clocked out of the DSP on the rising edge of SCLK, no glue logic is required to interface the DSP to the DAC. In the interface shown, the DAC output is updated using the LDAC pin via the DSP. Alternatively, the LDAC input could be tied permanently low and then the update takes place automatically when TFS is taken high. REV. 0 -11-
AD5530/ AD5531*
LDAC SYNC SDIN SCLK
PC6 PC7 MOSI SCK
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 9. AD5530/AD5531 to MC68HC11 Interface
AD5530/AD5531
The 68HC11 is configured for master mode, MSTR= 1, CPOL = 0, and CPHA = 1. When data is transferred to the part, PC7 is taken low and data is transmitted MSB first. Data appearing on the MOSI output is valid on the falling edge of SCK. Eight falling clock edges occur in the transmit cycle, so in order to load the required 16-bit word, PC7 is not brought high until the second 8-bit word has been transferred to the DAC's input shift register. LDAC is controlled by the PC6 port output. The DAC can be updated after each 2-byte transfer by bringing LDAC low. This example does not show other serial lines for the DAC. If CLR were used, it could be controlled by port output PC5. In order to read data back from the DAC register, the SDO line could be connected to MISO of the MC68HC11, with RBEN tied to another port output controlling and framing the readback data transfer.
APPLICATIONS Optocoupler Interface
ENABLE CODED ADDRESS EN DECODER* DGND
Serial Interface to Multiple AD5530s or AD5531s
Figure 11 shows how the SYNC pin is used to address multiple AD5530/AD5531s. All devices receive the same serial clock and serial data, but only one device will receive the SYNC signal at any one time. The DAC addressed will be determined by the decoder. There will be some feedthrough from the digital input lines, the effects of which can be minimized by using a burst clock.
AD5530/AD5531*
SCLK SYNC SDIN SDIN SCLK VCC VOUT
AD5530/AD5531*
SYNC SDIN SCLK VOUT
In many process control applications, it is necessary to provide an isolation barrier between the controller and the unit being controlled. Opto-isolators can provide voltage isolation in excess of 3 kV. The serial loading structure of the AD5530/AD5531 makes it ideal for opto-isolated interfaces as the number of interface lines is kept to a minimum. Figure 10 shows a 4- channel isolated interface to the AD5530/AD5531. To reduce the number of opto-isolators, if simultaneous updating is not required, then the LDAC pin may be tied permanently low.
VCC
*ADDITIONAL PINS OMITTED FOR CLARITY
AD5530/AD5531*
SYNC SDIN SCLK VOUT
AD5530/AD5531*
SYNC VOUT
CONTROLLER CONTROL OUT TO LDAC
SDIN SCLK
Figure 11. Addressing Multiple AD5530/AD5531s
SYNC OUT TO SYNC
Daisy-Chaining Interface with Multiple AD5530s or AD5531s
SERIAL CLOCK OUT
TO SCLK
A number of these DAC parts may be daisy-chained together using the SDO pin. Figure 12 illustrates such a configuration.
SERIAL DATA OUT
TO SDIN
OPTOCOUPLER
Figure 10. Opto-Isolated Interface
VDD
AD5530/AD5531*
SCLK SDIN SYNC SCLK SDIN SYNC SDO
R
AD5530/AD5531*
SCLK SDIN SYNC SDO
R
AD5530/AD5531*
SCLK SDIN SYNC SDO
R
TO OTHER SERIAL DEVICES
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 12. Daisy-Chaining Multiple AD5530/AD5531s
-12-
REV. 0
AD5530/AD5531
OUTLINE DIMENSIONS
Dimensions shown in millimeters
16-Lead Thin Shrink SO Package (TSSOP) (RU-16)
5.10 5.00 4.90
16
9
4.50 4.40 4.30
1 8
6.40 BSC
PIN 1 COPLANARITY 0.15 0.05 0.65 BSC 0.30 0.19
1.20 MAX SEATING PLANE 0.20 0.09
8 0
0.75 0.60 0.45
COMPLIANT TO JEDEC STANDARDS MO-153AB
REV. 0
-13-
-14-
-15-
-16-
C00938-0-5/02(0)
PRINTED IN U.S.A.

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